I remember reading a while ago that either asynchronous or synchronous resets are more efficiently implemented in FPGAs since the flip flops already have one, but the other would require additional logic.
Does anyone know which way round this is? Is this the same for Xilinx, Altera, Other..
When learning, I used to add an asynchronous clear and a synchronous reset to every FSM, just in case. Is there any benefit at all to this?
Thanks for any feedback!
Well, your best bet is to consult your specific FPGA vendor's documentation and white papers. In most of the professional design teams I've worked on, we used asynchronous resets to maintain maximum control. The choice between synchronous and asynchronous resets really depends on your design and application, however.
By the way, you might find this paper on the topic of resets from Sunburst Design interesting. Though it primarily addresses ASIC design and Verilog, it is a useful paper for understanding reset decisions in general.