for-loopverilogparity

Convert parity function from using unary XOR to a "for" loop

The following code obtains the even parity for the input A (i.e. parity = 1 if A contains 0 1’s or an even number of 1’s):

reg [7:0] A; 
wire parity;
assign parity = ~^A;

How can I use a for loop in a procedural block to obtain the same function?

Solution

  • Something like this should work. Basically you want to start at one end of the vector and work your way to the other end. Flipping the parity bit anytime you spot a '1'. If you don't spot any, parity is 1. If you spot an even #, parity will be 1 as well.

    integer i;
reg parity;

always (*) begin
    // Default values
    parity = 1'b1;
    
    for (i = 0; i < 8; i++)
        if (A[i])
            parity = ~parity;
end