I've got a DE10-Nano Cyclone V development board with 1 GB of external DDR3 RAM from Terasic and I want to implement a driver, which can manage the communication between Linux running on the ARM Cortex-A9 processor and the FPGA fabric of the Cyclone V.
With dma_alloc_coherent i allocate a certain amount of memory and write the hardware address to the FPGA module i programmed.
I then proceed to write an arbitrary number through the SDRAM AXI interface to the given address, but apparently neither the AWREADY, nor the WREADY signal ever get asserted by the SDRAM AXI-slave.
I've configured the SDRAM AXI Interface to run at 325 MHz, be 256 bit wide (datalength), have a 32 bit addressing length and to be an AXI3 slave. The SDRAM Interface is configured as TrustZone-aware device (ARM TrustZone setting)
I've also hardwired some other configuration lines to the AXI slave, which i'll be listing now:
assign axm_m0_arburst = 'd0;
assign axm_m0_arcache = 'd0;
assign axm_m0_arid = 'd0;
assign axm_m0_arlen = 'd0;
assign axm_m0_arlock = 'd0;
assign axm_m0_arprot = 'd0;
assign axm_m0_arsize = 'b101;
assign axm_m0_awburst = 'd0;
assign axm_m0_awcache = 'd0;
assign axm_m0_awid = 'd0;
assign axm_m0_awlen = 'd0;
assign axm_m0_awlock = 'd0;
assign axm_m0_awprot = 'd0;
assign axm_m0_awsize = 'b101;
assign axm_m0_wid = 'd0;
assign axm_m0_wstrb = 'hFFFFFFFF;
When looking at the FPGA bridge driver in Linux (/sys/class/fpga-bridge/br4) the state is shown to be 'enabled'.
What could be a reason for the bridge to still block communication?
Thanks for any help.
Problem solved:
Apparently even though Linux said the bridges are enabled, they weren't.
One has to write certain configuration bits into the configuration fabric of the HPS, otherwise the module wont work.
1. Generate a handoff folder with Quartus assemble step. This generates the configuration description for all bridges, among other stuff.
2. With bsp-editor generate and compile the first stage bootloader, which will have some global variables, that store the configuration values and make them available to bootscripts.
3. Generate a bootscript with this content:
echo -- Programming FPGA --
fatload mmc 0:1 $fpgadata soc_system.rbf;
fpga load 0 $fpgadata $filesize;
run bridge_enable_handoff;
mw $fpgaintf $fpgaintf_handoff;
mw $fpga2sdram $fpga2sdram_handoff;
go $fpga2sdram_apply;
mw $axibridge $axibridge_handoff;
mw $l3remap $l3remap_handoff;
#md $fpgaintf;
#md $fpga2sdram;
#md $axibridge;
setenv fdtimage soc_system.dtb;
setenv mmcroot /dev/mmcblk0p2;
setenv mmcload 'mmc rescan;${mmcloadcmd} mmc 0:${mmcloadpart} ${loadaddr} ${bootimage};${mmcloadcmd} mmc 0:${mmcloadpart} ${fdtaddr} ${fdtimage};';
setenv mmcboot 'setenv bootargs console=ttyS0,115200 root=${mmcroot} rw rootwait; bootz ${loadaddr} - ${fdtaddr}';
run mmcload;
run mmcboot;
The lines, that are commented, result in a crash, because apparently the data is unaligned, and these kind of accesses aren't allowed with the processor. I'll do further investigation on this issue.
For further reading on these topics I recommend these pages:
Cyclone V HPS Memory Map (Altera)
Tutorial on FPGA soft programming (Rocketboards)
How to enable HPS bridges (Altera)