Unresolved net/uwire cannot have multiple drivers

I am having some problems with the following code:

    module register_window(port_A, port_B, PD, CWP, A, B, C, loadRF, clk);

output reg[4:0] port_A;
output reg[4:0] port_B;
input [31:0] PD; 
input [1:0] CWP;    
input [4:0] A;    
input [4:0] B;
input [4:0] C;
input loadRF; 
input clk;

    reg ld; //enable 

    wire  [3:0] t;
    decoder_2x4 decoder2by4(CWP, t, loadRF);

    wire [31:0] bitDecoder1;
    decoder_5x32 decoder0(C, bitDecoder1, t[0]);

    wire [31:0] bitDecoder2;
    decoder_5x32 decoder1(C, bitDecoder2, t[1]);

    wire[31:0] globalReg0;
      assign ld = (bitDecoder1[0] == 32'b0 ||bitDecoder2[0] == 32'b0||bitDecoder3[0] == 32'b0||bitDecoder4[0] == 32'b0);
     registers g0(globalReg0, PD, ld, clk);      

    // G1
    wire[31:0] globalReg1;
      assign ld = (bitDecoder1[1]== 32'b0||bitDecoder2[1]== 32'b0||bitDecoder3[1]== 32'b0||bitDecoder4[1]== 32'b0);
     registers g1(globalReg1, PD, ld, clk);

     wire[31:0] globalReg2;
     assign ld = (bitDecoder1[2]== 32'b0||bitDecoder2[2]== 32'b0||bitDecoder3[2]== 32'b0||bitDecoder4[2]== 32'b0);
    registers g2(globalReg2, PD, ld, clk);

Basically what my code tries to do is set wire t as the output of a binary decoder as well as the input of other 5x32 decoders (some are omitted here). Then, depending on the values of the decoders it assigns a value to ld which is basically just an enable signal (if any of the decoder bits are 1, the enable is 1 otherwise, 0). Then these values go into a register, and are outputted by the wires (globalReg1, globalReg2, etc). They all use the same clock, if it matters.

The compilation errors I get are

testbench.sv:37: error: Unresolved net/uwire ld cannot have multiple drivers.

in each line of the assigns; assign ld = (bitDecoder1[1]== 32'b0||bitDecoder2[1]== 32'b0||bitDecoder3[1]== 32'b0||bitDecoder4[1]== 32'b0);

I also tried putting the above line between always @(*) begin and end statements (as I thought you always had to do that between logic parts of code) but then that simply gives me an error of:

testbench.sv:33: error: ld Unable to assign to unresolved wires.

If anyone could point me in the right direction, I'd be eternally grateful. Thank you!

First of all: the target of an assign must be a wire, not reg.

Second I can't find any definition of bitDecoder1 or bitDecoder2.
The name suggest they are bits but you are comparing them against 32 bits. That is confusing me somewhat but it is not essential to your problem.

... ld which is basically just an enable signal (if any of the decoder bits are 1, the enable is 1 otherwise, 0).

I can't match that with your code. There you have three registers (g0,g1,g2 and each needs an load enable. Thus you need an ld0, ld1, ld2.
Verilog is not like C where you can just re-use a variable multiple times. Just remember that it is a massive parallel language: all of the assigns everywhere in any file are executed at the same time.

Alternative you want all of g0,g1,g2 loaded if any of the 12 compares match. In which case you still need an ld0 ld1 and ld2 but you need to combines them with and OR-function:

assign ld = l0 | ld1 | ld2;