I've been reading about the classical ARM 7 microcontroller. There are two types of interrupts: IRQ and FIQ. FIQ allowing faster interrupt handling and having a higher priority than IRQ.
It states that modern ARM versions have nested interrupts.
Does this actually mean that the ARM 7 can only handle 2 interrupts assigned to the MCU, for example 2 edge triggered interrupts from an external source, and no more?
Thanks in advance
ARM7 would most likely have been used with a vectored interrupt controller - a component tightly coupled to the core, but not as tightly coupled as the modern interrupt controllers used or integrated with either Cortex-M (ARMv6-M, ARMv7-M and ARMv8-M) - which are integrated into the exception model, or the A-class interrupt controllers.
This older type of vectored interrupt controller would provide multiple inputs, with masking, and priority. It would raise an IRQ input to the core, and provide an address which the core could read as part of the common interrupt handler - this then branched to the exception specific handler. Note that at the architectural level, there would just be one IRQ interrupt - containing a hardware assisted jump table.
ARM7 also allowed a simpler interrupt architecture - the exact implementation being customised for the application. Most trivial (and maybe uncommon) would be to OR all of the interrupts together and require the interrupt handler to read the interrupt status of each peripheral to discover what is pending. This may seem very crude today, but it is still done to some extent - you might dedicate Rx and Tx interrupts for each I/O peripheral, yet combine all the error/overflow interrups for everything (since any of these mean game-over).
The trade-off between software and dedicated hardware handling of features is one example of how changing implementation costs can influence design decisions over time.