cpu-architectureinstructionsinstruction-setriscvmachine-instruction

What control lines are asserted/set to 1 when a load double word instruction is called?

enter image description here]Using this diagram, I am looking at this instruction to determine what control lines are necessary.

ld x5, 40(x9)

x5 = 0x000000ff

x9 = 0x00000fff

I am curious what control lines (RegWrite, MemRead, MemWrite, MemtoReg, Branch, Zero, ALUSrc) are asserted or set to 1 in order for this instruction to run, and why I understand the parts of the load double instruction to be ld RT, Disp(RA) - but what is required for execution and why? Thank you - resources on these things (that make sense to me) are extremely limited on the internet.

Solution

  • Its a LOAD instruction in which the memory address to be read is calculated by adding 40 to the contents of the register x9, the result is then stored in register x5.

    1. Instruction is writing to registers, therefore assert RegDst and RegWrite
    2. Instruction is required to add 40 to the contents of x5. Set ALUSrc to 1 to select 40 as one of the source.
    3. Assert MemReadas its a memory read. Also set MemtoReg to 1 so that mux will get the data from Memory rather than ALU.