verilogtest-benchicarus

Incomprehensible For Loop Icarus Verilog

I am trying to follow the basic example provided here. https://www.youtube.com/watch?v=13CzlujAayc&list=PLUtfVcb-iqn8ff92DJ0SZqwsX4W1s_oab&index=17

Here is my exact code

maj3.v

module maj3(Out, A, B, C);
    input A, B, C;
    output Out;

    wire AB, BC, AC;

        and(AB, A, B);
    and(BC, B, C);
    and(AC, A, C);

    or(Out, AB, BC, AC);

endmodule

testbench.v

module maj3_tb;

    reg a, b, c;
    wire out;

    maj3 DUT1(out, a, b, c);

    initial begin
        for (int i=0; i<8; i=i+1) begin
            #5 {a,b,c} = i;
        end
    end

    initial begin
        $monitor(a,b,c,out);
    end

endmodule

I am trying to compile with Icarus Verilog, but I am getting this error

testbench.v:9: syntax error
testbench.v:9: error: Incomprehensible for loop.

I have looked through my code a few times and I believe I have the same exact lines the lecturer has and I am using the same compiler. The only difference is that his is operating in a browser, whereas mine is in the Ubuntu terminal

Solution

  • I needed to look closely, but it looks like my default version was not matching his.

    enter image description here

    I reran the compile command with the same flags

    iverilog -Wall -g2012 -o maj3_test testbench.v maj3.v

    and it compiled fine. Not sure what the default version is or why it did not compile with that syntax.