verilogsystem-verilogcadencequestasimsynopsys-vcs

Is it possible to fully compile a module and then instantiate it in a testbench separately?


Is it possible to make a fully compiled and standalone version of an RTL module, like a snapshot in Cadence terms, and then later instantiate this compiled module into a testbench? Ultimately, running another compile step to create a final snapshot which contains the originally delivered snapshot but now instantiated in the testbench.

If so, are there any special considerations when compiling the original snapshot to enable this and how would you instantiate such a compiled object within a testbench?


Solution

  • Yes. But every simulation tool has slightly different approaches to the compilation flow. Most tools break this flow into a number steps: parsing, optimization, elaboration, and initialization (the snapshot you mention is the last step). Not all tools give you access to all the individual steps.

    There are several ways to achieve what you ask for, but the choice really depends on why you want to do this, and what limitations you are willing to work with.

    You can parse your module's source code into a library and then re-use that same library for compiling many different test benches. But usually the time consuming part is optimization.

    Questa provides what you are looking for in what they call the Pre-compiled Design Unit (PDU) flow. You can optimize your RTL module and save it back into a library, and Questa simply choses the optimized module instead of the un-optimized module during elaboration. The special considerations are that you need to preserve any signals from optimization that might have hierarchical references from the testbench.