In the AXIS stream speck the ACLK is defined as:
The global clock signal. All signals are sampled on the rising edge of ACLK.
Which means that it is assumed that AXIS master and slave are receiving the same ACLK.
Can you please help understand following:
1) If there is a ACLK slew on AXIS master and slave blocks,it is left under designer responsibility. Speck does not set any limitation on that. Is my understanding right?
2) The data transfer should be ACLK center aligned. So the developer should make the AXIS master to send clock center aligned data. Right?
3) How to make ACLK centric data transfer? Imagine you have global clock in the whole system, to make data to be transferred clock center aligned to that data, you need to generate new clock which has phase left shifted from your global clock. Any ideas how we can do it in FPGA?
I think the problem is in your understanding of English.
-centric is not the same as centre (or center).
Centric means here "The most important, where everything revolves around" It does not mean that the data is in the middle (centre) of the clock.
Thus in an AXI/AMBA system you must make sure all components use the same clock signal and all logic should run from the rising clock edge. That is in the same, standard, requirement of all synchronous logic.
Now to answer your questions:
1) If there is a ACLK slew on AXIS master and slave blocks,it is left under designer responsibility. Speck does not set any limitation on that. Is my understanding right?
You should not have clock skew. If you have, your are in deep trouble and yes, you have to solve that. Avoid it at all cost!
2) The data transfer should be ACLK center aligned. So the developer should make the AXIS master to send clock center aligned data. Right?
No. Everything is clocked of the rising clock edge. Which means the data will start changing shortly after that rising clock edge. You can see this in all the timing diagrams which are in the AXI/AMBA standard.
3) How to make ACLK centric data transfer? Imagine you have global clock in the whole system, to make data to be transferred clock center aligned to that data, you need to generate new clock which has phase left shifted from your global clock. Any ideas how we can do it in FPGA?
All you do is use the same ACLK signal everywhere. Do not shift the clock, do not generate a new clock.
Here are some Verilog modules I designed:
module ahbl_arbiter
#(parameter MA = 4 // Number of masters 2..8
)
( input clk, // System clock
input reset_n, // System reset
input clken, // Clock enable
....
module ahbl_splitter
#(parameter SL = 4, // Number of slaves 2..32
L2BS = 10 // Log 2 of block size 10 = 1K
)
( input clk, // System clock
input reset_n, // System reset
input clken, // Clock enable
....
module apb_bridge
#(parameter
NS = 8, // Number of slaves
L2BS = 10, // Log2 Address block assigned each peripheral
REG = 1'b0 // Register in rdata return path
)
( input clk, // System clock
input reset_n, // System reset
input clken, // Clock enable
...
If you use these they all have the same clock:
ahbl_arbiter
ahbl_arbiter_0 (
.clk (aclk), // System clock
.reset_n (reset_n), // System reset
.clken (clken), // Clock enable
....
apb_bride
apb_bride_0 (
.clk (aclk), // System clock
.reset_n (reset_n), // System reset
.clken (clken), // Clock enable
....
ahbl_splitter
ahbl_splitter_0 (
.clk (aclk), // System clock
.reset_n (reset_n), // System reset
.clken (clken), // Clock enable
....