lattice mackXO3 board output transient

I have a lattice MachXO3L starter kit and I'm having some trouble with inputs, I think. I'm tried reducing the code only to read 4 switches (MachXO3 Starter Kit User’s Guide page 26) and light 4 LEDs according to the state of the switch. The problem is the LEDs seem to be half off. I tried adding 'reveal' and it appears that I'm not getting any change from the switches when I expect change. I set the spreadsheet I set it the same as in the example. I'm still learning VHDL, this is the first time I'm actually trying to connect something to it and the example is on Verilog, so I can't really check what I'm doing wrong. I'm probably missing something basic, but I don't know what.

Top File:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity TOP is 
    GENERIC(
        DATAWIDTH   : natural := 4
    );
    PORT(
        -- Input Buffer --
        ADCInputBuffer : IN STD_LOGIC_VECTOR (DATAWIDTH-1 downto 0);
        OUTPUT : OUT STD_LOGIC_VECTOR (DATAWIDTH-1 downto 0);
        ADC_SRT     : OUT STD_LOGIC
    );
end TOP;

architecture ADReader of TOP is
    SIGNAL INTERNAL_CLOCK : STD_LOGIC;
    SIGNAL CLOCK          : STD_LOGIC;
    SIGNAL CLOCK_65       : STD_LOGIC;

    -- BUFFER --
    signal adcInPut : std_logic_vector(DATAWIDTH-1 downto 0);   

    ---------------------------------------------------
    --  Internal Clock. Mach0X3                      --
    ---------------------------------------------------
    COMPONENT OSCH is
        GENERIC(NOM_FREQ: string := "133.00"); --133.00MHz, or can select other supported frequencies
        PORT(
            STDBY    : IN  STD_LOGIC;     --'0' OSC output is active, '1' OSC output off
            OSC      : OUT STD_LOGIC;     --the oscillator output
            SEDSTDBY : OUT STD_LOGIC      --required only for simulation when using standby
            );    
    END COMPONENT;
    ---------------------------------------------------
    --  Internal Clock multiplier. Mach0X3           --
    ---------------------------------------------------
    COMPONENT MASTERCLOCK is
        PORT(
            CLKI       : IN  STD_LOGIC;     --'0' OSC output is active, '1' OSC output off
            CLKOP      : OUT STD_LOGIC;     --the oscillator output 260MHz
            CLKOS      : OUT STD_LOGIC     --the oscillator output for adc 65Mhz
            );    
    END COMPONENT;
    ---------------------------------------------------
    --  Read data In                                 --
    ---------------------------------------------------
    COMPONENT InputBuffer is
        GENERIC(n: natural :=DATAWIDTH );
        PORT(
            clk    : in STD_LOGIC;
            CLK65  : IN STD_LOGIC;
            En     : in STD_LOGIC;
            STRT   : OUT STD_LOGIC;
            Ipin   : in  STD_LOGIC_VECTOR (n-1 downto 0);
            Output : out  STD_LOGIC_VECTOR (n-1 downto 0)
        );
    END COMPONENT;

    begin
        -- System Clock 
        OSC: OSCH
        GENERIC MAP (NOM_FREQ  => "133.0") 
        PORT MAP (STDBY => '0', OSC => INTERNAL_CLOCK, SEDSTDBY => OPEN);

        -- System Clock Multiplied
        OSCmain: MASTERCLOCK
        PORT MAP (CLKI => INTERNAL_CLOCK, CLKOP => CLOCK, CLKOS => CLOCK_65);

        -- Gets data from ONE ADC
        ADCIn: InputBuffer
        GENERIC MAP (n => DATAWIDTH)
        PORT MAP( clk => CLOCK, CLK65 =>CLOCK_65, EN =>'0', Ipin => adcInPut, Output => OUTPUT, STRT => ADC_SRT );
        adcInPut <= ADCInputBuffer;
end ADReader;

InputBuffer:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity InputBuffer is
    generic(n: natural :=4 );
    Port (  
            clk    : in STD_LOGIC;
            CLK65  : IN STD_LOGIC;
            En     : in STD_LOGIC;
            STRT   : OUT STD_LOGIC;
            Ipin   : in  STD_LOGIC_VECTOR (n-1 downto 0);
            Output : out  STD_LOGIC_VECTOR (n-1 downto 0)
        );
end InputBuffer;

architecture Behavioral of InputBuffer is
    signal temp : STD_LOGIC_VECTOR(n-1 downto 0);
    SIGNAL CLK2 : STD_LOGIC;
begin
    -- invert the signal from the push button switch and route it to the LED
    process(clk, En)
    begin
        if( En = '1') then
            temp <= B"0000";
        elsif rising_edge(clk) then
            temp <= Ipin; 
        end if;
    end process;
    Output <=  temp;
    STRT <= CLK65;
end Behavioral;     

this is the setting for MASTERCLOCK generated by lattice diamond: this is how the pins are setup: and here is the netlist generated by lattice-diamond:

here I'm just trying to have a static output:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity TOP is 
	GENERIC(
		DATAWIDTH   : natural := 4
	);
	PORT(
		OUTPUT : OUT STD_LOGIC_VECTOR (DATAWIDTH-1 downto 0)
	);
end TOP;

architecture ADReader of TOP is
	begin
		OUTPUT <= B"1010";
end ADReader;

Page 15 of the user guide (The link you provided) mentions different LED pins: H11,J13,J11,L12 which you have as ADC input. I think you might have swapped some pins around...