[SOLVED] Include Makefile and Echo Variables Inside Multiple Makefiles

Include Makefile and Echo Variables Inside Multiple Makefiles

Inside a Makefile I have recently had to look at, it includes this include $(MAKERULES)

Now to me, I would think somewhere at the top of the makefile it has MAKERULES = xyz but it does not. So I print out MAKERULES

test:

    @echo "Rules: $(MAKERULES)"

Then I do make test. It runs and it prints out another Makefile Location, Makefile2.

X/Y/Z/Makefile2 path. I go inside this Makefile and attempt to write out some echo statements so I can see what is printing, but nothing prints out.

Is it possible to print out variables from another Makefile (Makefile2) that my local Makefile (Makefile) references to?

Solution

Yes, it is possible. You haven't shown us your attempt to display those variables, so we can't tell you why it didn't work. (Well, I can't.)

Here is how I'd do it:

$(info the variable FOO contains $(FOO))

If you want to do this for several variables:

$(foreach X, FOO BAR BAZ, $(info $(X) is $($(X))))

And the list of all currently defined global variables is .VARIABLES, so you can use "$(.VARIABLES)" in place of "FOO BAR BAZ" to print all of them.