I am trying to implement a reconfigurable module which changes its configuration according to user setup. Where I will have a huge if else ladder. When an user decides to shift the bits by 4 bits to right, all the values inside of the if else condition ladder also should change accordingly and the user does not have to change each and every value manually. One central change would be enough to make this happen.
I have started with trying it out with function first, which is why I am yet to write finalize anything but having trouble with the error.
Below you will find out the rtl and tb. I need help with two things:
(1) Why I am getting this error in Cadence ncelab software? (2) What is the best way to adjust the values that exist inside of the "if ... else" condition? Because I will have a huge if else ladder.
RTL:
module function_trial (clk,value_in, value_out
);
input clk;
input value_in;
output value_out;
reg [31:0] value_in;
reg [31:0] c;
reg [31:0] value_out;
function [31:0] truncation; //The function truncates the last 4 lsbs
input [31:0] trunc_in;
begin
truncation = trunc_in >> 4;
end
endfunction
always @(value_in) begin
c = 32'h00000000;
if (value_in >= truncation(32'h08000000) && value_in < truncation(32'h0A000000)) begin
c = 32'h00000001;
end else if (value_in>= truncation(32'h0A000000) && value_in < truncation (32'h0C000000)) begin
c = 32'h00000002;
end
end
assign value_out=c;
endmodule
TB
`timescale 1ns/10ps
module tb_function_trial (
);
reg clk;
reg [ 31 : 0 ] value_in;
wire [ 31 : 0 ] value_out;
function_trial function_trial_i (
.clk(clk),
.value_in(value_in),
.value_out(value_out)
);
parameter CLKPERIODE = 20;
initial clk = 1'b1;
always #(CLKPERIODE/2) clk = !clk;
initial begin
value_in = 32'h00810000;
#10
value_in = 32'h00B00000;
#50 $finish();
end
`include "testcase.v"
endmodule
It is possible that I could not ask the question properly. Kindly let me know if you need more clarification.
I see two errors in the code.
reg [31:0] value_in; is wrong because it is an input and an input can not be of type 'reg'. You must change that to `wire'.
reg [31:0] value_out; is wrong because you are using 'assign'. The target of an assign must be a wire not a reg. so that one also needs to change to `wire'.
I can't match these error types to the error message in your title. I suspect these errors prevented the module from being generate and that may be the cause of the error message your have listed. In which case please check for additional error messages elsewhere.