logicdelaycircuit

What are the difference in delay times of the basic AND, OR, NOT, NAND, NOR, XOR, XNOR gates?


1-1 What are the difference in delay times of the basic logic gates?

I found that NAND and NOR gates are preferred in digital circuit design for shorter delay time and that AND and OR gates might even be implemented with NOT and NAND/NOR gates.

1-2 Are there set or known difference in delay time between AND, OR, NOT gates?


Solution

  • If you look at how these different gates are constructed you can see some of the reasons for differences. An inverter consists of one pull-up transistor and one pull down transistor. This is the simplest gate and is therefore potentially the fastest. A NAND has two pull-down devices in series and two pull-up transistors in parallel. The NOR is basically the opposite of the NAND. And yes: AND is usually just NAND + inverter.

    The on resistance of a path will be higher with two transistors in series (making it slower), and the number of transistors connected to a single node will increase the captive load (making it slower). You can make things faster by using larger transistors (with lower on resistance) but that increases the load of whatever cell is driving it, which slows that cell down.

    It is a big optimization problem which you probably shouldn't try to solve yourself. That is what the EDA tools are for.