I read the answer the similar question at How ram addresses are differentiated from memory map address but I am still confused.
Assuming a System attaching 4GB RAM with some memory mapped peripherals attached, then the only RAM space I can use is 4GB minus amount of memory mapped space?
For example, a GPIO is mapped at address 0x500 then there is no way to use RAM address 0x500? I believe it is possible(hopefully?) if the MMU exists and is enabled, but otherwise I have no idea.
You tagged ARM and other processors are not necessarily different.
Normally some percentage of the address space is carved out for memory mapped I/O, gpio, uart, nvic, etc. With arm you will have some internal address space that doesnt make it to the axi/amba bus(ses) for the chip vendor.
So if you wanted to use an ARM with a 32 bit address bus then hooking up 4GB flat is a waste of time. You can certainly hook up more (I have an arm11 with 24GB)) but it is not linear you have to have an address scheme like PCIe has, where you point a window of the address space you can get into an address space beyond that (again think PCIe but reality not the illusion that they try to present in x86).
But you are overcomplicating this. Particularly with an ARM where it is all documented. You have a core you are a chip vendor you buy this core it has an address bus (see the amba/axi documentation) you hook up to that address bus if it is a cortex-m they have some guidelines as to where to put ram and rom and keep out of the way here. For the full sized arms its mostly fair game, you provide the base address to the core where certain peripherals are mapped (think nvic, timers, etc.
Instead of like the cortex-m where the systick timer base address is hardcoded in the design, you feed the core the base address in your address space where the internal items life PERIPHBASE or some such signal/bus name). Beyond that it is the whim of the chip vendor as to how to divide up that address space, the arm can boot typically in one of two addresses but of course you can have as many address layers as you want, and for each layer have a conversion/translation to that address space. This includes peripherals, memory (ram/rom/flash) usb, pcie, etc address spaces, etc.
So it could be like a PC where the pcie window takes away the one or two gig of ram at that same space and you simply lose that memory, but in that case you are thinking about it a bit wrong because those are different address spaces/layers. Some PCs once 64 bit dominated over 32 bit and even though 32 bit isn't completely dead but we can now have bioses that default to 64 bit and allowing the pcie window to be above the memory instead of cutting a hole in it.
The nice thing about buying a core like arm or mips that you can to some extent if not completely design the address space however you like, don't have to conform to anything, etc.
There is no one answer to your question you need to specify the specific chip and board (and version of that system) to have this conversation, and if it were a real, available product, they wouldn't have bothered unless there was a windowed address scheme. Folks like to think the segment offset thing was bad but it still exists in most usable systems we just can't use those terms any more, and we don't always have segment registers but we still have the address space carved out and windowed. MMUs make this much easier to segment the address spaces but make them look linear.