shellmakefiledollar-sign

Universally escape dollar sign


I'm working on embedded project, which consists of my own code as well as 3rd party libraries and executables. To build all the parts consistently, I've written a script, which sets environment variables for cross-compilation (CC, CXX, CFLAGS, etc.). Among others it sets LDFLAGS to pass the rpath flag to linker. The rpath value contains $ORIGIN token, which must not be expanded and must be seen by linker and written to output binary as is. I then build several needed 3rd party projects using the environment set by the script. The projects uses different build systems (make, CMake, others maybe). Because of this and maybe because of the build scripts written in different ways, the dollar sign is expanded differently. I.e., whatever escaping I try, I get different results in different projects (e.g., $$ORIGIN, RIGIN, empty string), but never I managed to get the same $ORIGIN value in all the binaries. Is there a universal way to escape dollar sign so that it will work the same in at least make and shell, but in any combination?


Solution

  • This is how I've finally solved this problem. In addition to the previous environment variables, needed to build for my platform, I've added two more:

    ORIGIN=$ORIGIN
    O=$$O
    

    The former is to workaround shell expansion, and the latter is to workaround makefile expansion. With this fix, variables are resolved to themselves. Yes, this does not look like an ideal solution, looks more like a hack, but it works so far allowing me to avoid adapting my build environment for every third party project I use.