[SOLVED] How are rs1 & rs2 fields for floating point registers (f0-f31) encoded in RISC-V Instructions?

How are rs1 & rs2 fields for floating point registers (f0-f31) encoded in RISC-V Instructions?

The Integer register encoding corresponds to their numeric names (0-31, for x0-x31). What is this encoding for f0-f31?

I am trying to write a disassembler.

Solution

The floating-point registers are encoded in the same way. The processor knows whether to use an integer register or a floating-point register by the nature of the instruction.

RISC-V specifications are at https://riscv.org/specifications/. As a sample for one type of instruction, in The RISC-V Instruction Set Manual, Volume I: User Level ISA, version 2.2, May 7, 2017, section 8.6, “Single-Precision Floating-Point Computational Instructions” says:

Floating-point arithmetic instructions with one or two source operands use the R-type format with the OP-FP major opcode. FADD.S, FSUB.S, FMUL.S, and FDIV.S perform single-precision floating-point addition, subtraction, multiplication, and division, respectively, between rs1 and rs2, writing the result to rd.

The R-type format is shown in 2.2, “Base Instruction Formats.” A diagram there shows rs1, rs2, and rd are bits 19 through 15, 24 through 20, and 11 through 7, respectively.