fpga pins are deactivated
I have been developing an IP and it was working just fine until I used it in a project.
After that two of fpga's output pins didn't work at all ! After some investigations I just realized that, in design summary these two pins reported under reg(s), valued ''off''. I think that somehow these two pins switched off.
Can anyone tell me how can I switch a pin off and on, and what makes it behave that way?
These pins are doing a simple job just turning a led on and off and they are working fine when I am testing IP, and just in the bigger project switched off.
Solution
The "OFF" in Reg (s) column doesn't mean that pin is turned off.
It means that the IOB is configured to use "Output Flip Flop" :)
Other modes might include IFF, ODDR, ENFF, etc.
- Vitis HLS change of datatype makes variable unused
- Fifo initialization and data transmission in Vitis
- Declaring variables in Verilog for loop
- Yosys/nextpnr timing report for Lattice ECP5 FPGA?
- Mismatch between behavioral simulation and post-synthesis functional simulation in vivado
- Why am I not able to write to/read from custom AXI lite peripheral's registers
- Where to force xilinx ISE to use block-rams?
- SystemVerilog inheritance, aggregated classes and parent function call
- When should I use a function over a procedure?
- How to program Lattice iCE40 ultra with a microcontroller
- How to test PS/2 device
- VHDL Hierarchical Reference within/to Generate Statement(s)
- Is it possible to tie ports high always high outside of top module?
- Vivado Error: [DRC MDRV-1] Multiple Driver Nets
- How to initialize contents of inferred Block RAM (BRAM) in Verilog
- PCIe BAR access
- IO placement is infeasible error in Vivado
- Verilog module always going to default case when assigning value to input
- Can SYSCLK be included in FPGA Xilinx vivado testbenches?
- Quartus-FPGA: Disable Path Optimization
- VHDL 10^x LUT With-Select
- How to initialize coefficients of a large digital filter in Verilog?
- Yosys optimizes away ring oscillator on ice40 FPGA
- how to add python in xilinx vitis
- Determine if a module in SystemVerilog is synthesizable
- Verilog: mapping an memory array
- pci_enable_device() fails after remove/rescan
- Is it possible to restrict UDP packets being sent to an FPGA to a single host?
- Module that converts ASCII to 7-segment display using FPGA
- Should my PC recognize my Arty A7-100T FPGA?