How does perf use the offcore events?

Some built-in perf events are mapped to offcore events. For example, LLC-loads and LLC-load-misses are mapped to OFFCORE_RESPONSE. events. This can be easily determined as discussed in here. However, these offcore events require writing certain values to certain MSR registers to actually specify a particular event. perf seems to be using an array called something like snb_hw_cache_extra_regs to specify what values to write to which MSR registers. I would like to know how this array is used. Basically I want to know how to determine the specific offcore event that a perf event is mapped to by looking at the source code.

The array of the offcore PM MSRs is stored here for SnB, other architectures are close.
The macro INTEL_UEVENT_EXTRA_REG is here and it just sets the msr to the second parameter, the config_mask to 0x000000FFULL and the valid_mask to the third parameter (the first being the event to program the the associated ordinary PMR with).

The values of the snb_hw_cache_extra_regs is just what it's going to be written in the selected PM MSR¹.
This array is looked up here and used here to select the first PM MSR matching, where the config arg comes from the array hw_cache_event_ids.

So it's basically a loop testing a couple of bitmasks until a compatible PM MSR is found, I think you can just skip that and look at the values stored in the snb_hw_cache_extra_regs array.

¹ Since the macro defined to make the values in snb_hw_cache_extra_regs are never reused in source and the values maps directly to the MSR layout documented in the Intel manuals, I didn't bother verifying this statement.