I found an issue in an Electronics Design Automation proprietary language and decided to look it up to see how things were handled in SystemVerilog and found that the LRM just skated over a topic that needs clarification.
I tried to find a blog or email on the IEEE and Accellera sites but failed.
My question is: how do I contact that IEE group working on SystemVerilog, to indicate an issue that could do with clarification in their spec?
Thanks :-)
I am a member of the IEEE working group.
The IEEE has a bug tracking system that you visit as a guest to see if the issue is already reported. You can also post your issue on a popular SystemVerilog forum like https://verificationacademy.com/forums/systemverilog or https://www.quora.com/topic/SystemVerilog and there is usually someone for the group there to respond.