I read about these two types of architecture and somewhere on the internet someone said that systems using Von Neumann architecture are faster than the ones using Harvard architecture. I tried searching for why this is the case but I was yet to find a explanation that clarified the things for me.
In my understanding: - in a Von Neumann architecture the CPU can do one operation at a time meaning it can fetch data or fetch an instruction from memory in one cycle. So to perform some sort of operation on a data it needs 2 cycles(one to fetch the data and one to fetch the instruction). - in a Harvard architecture the CPU can fetch both data and an instruction in the same clock cycle since there are 2 separate memory blocks and two separate sets of data address busses
So if the HV architecture can do the same thing that VN does in one cycle why is it slower? Doesn't less cycles used for one thing means it should be faster than the other? Please go easy on me I'm a noob in embedded systems. Thank you for reading my post!
In a von Neumann architecture, the CPU operates sequentially, e.g. it does fetch instruction, decode it, fetch operands (data), compute result, and store it. All these steps use the same memory channel.
A Harvard architecture has two memory channels, one for instructions, and one for data. It has an advantage over the von Neumann architecture, if the CPU supports pipelining, i.e. while instruction x, that has been decoded already, is fetching operands (data) over the data channel, instruction x+1 is fetched at the same time over the instruction channel.
So, if the CPU is pipelined, a Harvard architecture is faster than a von Neumann architecture.