system-verilogsynopsys-vcs

Connect different port width


Suppose my module has a 8-bit input and 8-bit output

module MyModule (input logic [7:0] in, output logic [7:0] out);
    ...
endmodule : MyModule

If I want to connect a 1-bit input in and leave the other bits as zero, the following works:

MyModule (.in({7'b0, a}), .out(b))

How can I do the same if I want a 1-bit output, ignoring the other bits? Something like this

MyModule (.in(a), .out({7'b0, b}))

vcs says its invalid, and connecting b directly gives a warning. I'd ideally like a solution that doesn't throw warnings.

Here's what I've thought of:

Any solution better than these?


Solution

  • You could use the streaming operator:

    MyModule M (.in(a), .out({<<{b}}));
    

    But I think your first idea is the most straightforward.