Is there a time when processor use ram directly for its operations, without the involvement of cache memory? OR its like Processor always takes data from Cache and cache gets from Ram?
Not normally, no, unless software purposely bypasses or disables cache on modern CPUs.
With latency to DRAM being maybe 70 ns, that's 280 cycles on a 4GHz CPU. That's enough time for a Skylake CPU to execute ~1100 instructions at 4 instructions per cycle. But its limit on memory-parallelism is about 12 outstanding cache misses. So cache is very very important for performance, even with out-of-order execution.
Fun fact, though: Yes, the MMU in P5 Pentium CPUs and earlier bypassed cache when accessing the page tables after a TLB miss. Source: an answer from Andy Glew, former Intel CPU architect who worked on P6: Are page table walks cached?
Modern CPUs including modern x86 do access page tables through their data caches, though: What happens after a L2 TLB miss?
x86 has movnt instructions for cache-bypassing stores, to avoid cache pollution for big memset. There are tradeoffs for bandwidth. See Enhanced REP MOVSB for memcpy for more about NT stores and no-RFO stores from rep movsb on CPUs with the ERMSB feature. Probably some other architectures have similar features.
You can also set a range of physical address space to be uncacheable. (Or on x86, per 4k virtual page with Page Attribute Table settings in the page table entries.)
Normally this is done for MMIO regions (memory-mapped I/O), where instead of DRAM the "memory" is actually I/O registers on devices like network cards. So every load/store is a visible side-effect, and speculative prefetch must be disallowed. (And every store must result in a separate off-core write transaction, e.g. a PCIe message.)
Also, x86 CPUs have control registers that let you disable cache, making them extremely slow. How can the L1, L2, L3 CPU caches be turned off on modern x86/amd64 chips?. Again, I assume other ISAs have similar features.