I just started learning Verilog and decided to make a 4 bit adder. To create this 4 bit adder, I first built a half_adder module, then a full_adder module which uses the half_adder module. In the 4 bit adder I use 4 full_adder modules. Up to this point everything compiles and simulates with Verilator. I wrote some tests and checked that all outputs were correct.
After being done with the 4 bit adder, I thought of creating a small ALU which uses the 4 bit adder for additions. Now when I create a submodule of the 4 bit adder in the ALU module, I get verilator errors.
The 4 bit adder looks like:
`default_nettype none
module adder_4_bit(
i_a,
i_b,
o_sum,
o_carry
);
input [3:0] i_a;
input [3:0] i_b;
output [3:0] o_sum;
output wire o_carry;
wire internal_carry1;
wire internal_carry2;
wire internal_carry3;
full_adder full_adder1(
.i_a ( i_a[0] ),
.i_b ( i_b[0] ),
.i_carry ( 1'b0 ),
.o_sum ( o_sum[0] ),
.o_carry ( internal_carry1 )
);
full_adder full_adder2(
.i_a ( i_a[1] ),
.i_b ( i_b[1] ),
.i_carry ( internal_carry1 ),
.o_sum ( o_sum[1] ),
.o_carry ( internal_carry2 )
);
full_adder full_adder3(
.i_a ( i_a[2] ),
.i_b ( i_b[2] ),
.i_carry ( internal_carry2 ),
.o_sum ( o_sum[2] ),
.o_carry ( internal_carry3 )
);
full_adder full_adder4(
.i_a ( i_a[3] ),
.i_b ( i_b[3] ),
.i_carry ( internal_carry3 ),
.o_sum ( o_sum[3] ),
.o_carry ( o_carry )
);
endmodule
The ALU (for now) looks like this. I still need to implement the optcode select etc, but even creating the 4 bit adder submodule already resulted in errors...:
`default_nettype none
module alu_4_bit(
i_a,
i_b,
i_opt,
o_result,
o_status
);
input [3:0] i_a;
input [3:0] i_b;
input [3:0] i_opt;
output [3:0] o_result;
output [4:0] o_status;
adder_4_bit adder_4_bit_inst(
.i_a(i_a),
.i_b(i_b),
.o_sum(o_result),
.o_carry(o_status[0])
);
endmodule
When running the command
verilator -Wall -cc alu_4_bit.v
I get the following errors:
verilator -Wall -cc alu_4_bit.v
%Error: adder_4_bit:5: Unterminated string
%Error: adder_4_bit:11: Unterminated string
%Error: adder_4_bit:27: Unterminated string
%Error: adder_4_bit:28: Unterminated string
%Error: adder_4_bit:31: Unterminated string
%Error: adder_4_bit:40: Unterminated string
%Error: adder_4_bit:44: Unterminated string
%Error: adder_4_bit:58: Unterminated string
%Error: adder_4_bit:60: Unterminated string
%Error: adder_4_bit:66: Unterminated string
%Error: adder_4_bit:70: Unterminated string
%Error: adder_4_bit:72: Unterminated string
%Error: adder_4_bit:78: Unterminated string
%Error: adder_4_bit:79: Unterminated string
%Error: adder_4_bit:81: Unterminated string
%Error: adder_4_bit:86: Unterminated string
%Error: adder_4_bit:93: Unterminated string
%Error: adder_4_bit:119: Unterminated string
%Error: adder_4_bit:121: Unterminated string
%Error: adder_4_bit:124: Unterminated string
%Error: adder_4_bit:131: Unterminated string
%Error: adder_4_bit:132: Unterminated string
%Error: adder_4_bit:133: Unterminated string
%Error: adder_4_bit:134: Unterminated string
%Error: adder_4_bit:135: Unterminated string
%Error: adder_4_bit:139: Unterminated string
%Error: adder_4_bit:141: Unterminated string
%Error: adder_4_bit:143: Unterminated string
%Error: adder_4_bit:144: Unterminated string
%Error: adder_4_bit:146: Unterminated string
%Error: adder_4_bit:148: Unterminated string
%Error: adder_4_bit:150: Unterminated string
%Error: adder_4_bit:157: Unterminated string
%Error: adder_4_bit:160: Unterminated string
%Error: adder_4_bit:162: Unterminated string
%Error: adder_4_bit:164: Unterminated string
%Error: adder_4_bit:165: Unterminated string
%Error: adder_4_bit:1: syntax error, unexpected $undefined
%Error: Exiting due to 38 error(s)
%Error: Command Failed /usr/local/bin/verilator_bin -Wall -cc alu_4_bit.v
The strange thing is that these errors seem to come from the adder_4_bit.v while I already compiled and simulated it with verilator. I even made sure it worked correctly.
What could be the issue here?
I did not get such warnings when I tried to compile it with verilator, however I got some other warnings:
alu_4_bit.v:12: Signal is not used: i_opt
I commented out input[3:0] i_opt and i_opt's definition in module I/O and then I got this warning.
%Error: alu_4_bit.v:20: Illegal bit or array select; type does not have a bit range, or bad dimension: type is logic
I replaced output[3:0] o_status with output o_status and removed the bit select from .o_carry(o_status[0]) so that it is .o_carry(o_status) now.
After these, the design compiled with my version (4.004) of verilator. I hope these help you as well.