assemblycpu-architecture32-bit16-bit68hc11

How 32-bit word would be stored in 16-bit architecture that does not detect overflow?


How would a 32-bit numeric codeword be stored in a hypothetical 16-bit architecture if this system cannot detect the overflow?

How would it be stored in a real 68HC11 system?

What confuses me is that in the system that does not detect the overflow, I am not sure if it is possible to store the value larger than 16 bits at all?


Solution

  • how a 32-bit numeric codeword would be stored in a 16-bit architecture ...

    Simply storing information does not require any features of the CPU.

    For storing N bits of data, you require N/8 bytes of memory.

    It is the software (and not the hardware) that must "know" if four bytes contain one 32-bit word, a 32-bit floating-point value, two 16-bit words, 4 8-bit words or 32 single bits.

    If you write a program in assembler, you have to write the program accordingly. If you use some programming language, the compiler must do this.

    ... if this system cannot detect the overflow?

    Calculation (especially adding) is a different thing. If you refer to the "carry flag" by the word "overflow":

    You can manually check for a carry: If you add two numbers and there is a carry out, the sum will be smaller than each of the two summands. If there is no carry, the sum will be larger or equal to each summand.

    When you perform a 64-bit addition on a MIPS CPU (a 32-bit CPU not supporting a carry flag) using the GCC compiler, this check will be done. Here the pseudo code:

    sum_low  = a_low + b_low
      // The CPU does not support carry:
    sum_high = a_high + b_high
      // Simulate carry:
    if(a_low > sum_low) sum_high = sum_high + 1
    

    How would it be stored in a 6811 system?

    As far as I know the 6811 uses "big endian" storage. This means that the CPU itself stores 16-bit words (like the program counter) in a way that the high 8 bits are stored at an address N and the low 8 bits are stored at address N+1.

    For this reason, most compilers would also store a 32-bit word "big endian": The high 8 bits are stored at address N and the low 8 bits are stored at address N+3.

    The 6811 definitely supports a "carry flag", adding with carry-in and an "overflow flag". So an 6811 is not an example of a CPU "not detecting an overflow". See old_timer's answer how adding works on CPUs that have overflow and carry.