I have a MachXO3 chip. Family datasheet is available here: http://www.latticesemi.com/~/media/LatticeSemi/Documents/DataSheets/MachXO23/DS1047-MachXO3-Family-Data-Sheet.pdf?document_id=50121
The datasheet says that EBR is composed of 9-kbit on page 2-10. But the table 1-1 on page 1-2 lists numbers that are not dividable by 9 at all...
Also, I have the following code:
reg [7:0] lineB0[1:0][127:0];
reg [7:0] lineB1[1:0][127:0];
and the report says that it takes 4 EBR. That sounds completely un-optimized. Why is that? How can I craft my table of 2*(2*128) bytes = 512 bytes = 4096 bit = 4kbit which should hold in 1 EBR?
The automatic inference algorithm seems to be not always super efficient. I generally would recommend to use the IPexpress to create a RAM or ROM if ressource usage is an issue. The tool report a resource use of 1 EBR for a 512*8 dual pipeline ram (RAM_DP). Depending on the organisation/application of your RAM a 128*(8+8) layout might be a good alternative under the assumption that you want to read always the same index for lineB0 and lineB1.
A friendly reminder: premature optimization is the root of all (or at least many) evil. So investing your time in other topics might be more worthwhile if the used amount of memory EBR is actually no limitation right now.