[SOLVED] I put scrambler and descrambler module in vhdl respectively but the result of descrambler is not as same as the input of scrambler

I put scrambler and descrambler module in vhdl respectively but the result of descrambler is not as same as the input of scrambler

I have coded the scrambler of the 10G Ethernet. I found out the polynomial from the ieee802.3ae standard. in the document was figured a block diagram(49-10,49-8). when I put scrambler and descrambler module respectively. I can not see the input of scrambler at the output of descrambler.where is my problem? and how can I fix that?

I have already tried a reverse bit order but it doesn't help me. :(

--I0 is the descrambler input --my descrambler

    O0(  38 downto  0 ) <= I0(  38 downto  0 ) XOR I1( 63 downto 25 ) XOR 
    I1( 44 downto  6 );
    O0( 57 downto  39 ) <= I0( 57 downto  39 ) XOR I0( 18 downto  0 ) XOR 
    I1( 63 downto 45 );
    O0( 63 downto 58 ) <= I0( 63 downto 58 ) XOR I0( 24 downto 19 ) XOR 
    I0(  5 downto  0 );
    I1  <= I0;

--I0 is the scrambler input --my scrambler

    OO1 <= O0;
    O0( 38 downto  0  ) <= OO1( 63 downto 25 )  XOR OO1( 44 downto 06 ) 
    XOR I0( 38 downto  0  );
    O0( 57 downto  39 ) <= O0 ( 18 downto  0 )  XOR OO1( 63 downto 45 ) 
    XOR I0( 57 downto 39  );
    O0( 63 downto  58 ) <= O0 ( 24 downto 19 )  XOR  O0( 5  downto 0  ) 
    XOR I0( 63 downto 58  );

my expected result is the similarity between data that I fetch into the scrambler and result of descrambler.Figure 49-8 scrambler ieee802.3ae Figure 49-10 descrambler ieee802.3ae

Solution

I have solved my problem, my problem was a misunderstanding of Fig49-8. I implement 64-bit scrambler in one clock.