Whenever I find something on hazard, I find it in the context of RISC processors like MIPS.
Are WAW and WAR hazards unique to RISC processors?
Or, CISCs can also encounter those hazards?
No, WAW and WAR hazards are common to any system in which read and write transactions of data are potentially executed in an order different than the instructions appear (Not just processors even!).
MIPS (and sometimes RISCV) are just frequency used examples as they are easier to understand and are good learning processors.