system-verilogsystem-verilog-assertions

Indexing array of instances and interfaces


I have an array of interfaces. I know that array of instances and interfaces are not like ordinary arrays that can be indexed with a variable; here we have to index with a constant (or using generate block), and that is exactly the problem.

I am using a generate block to store the destination slave id to which a master is sending the packets according to the address provided. Here m_ahb is the array of master interfaces. I also got the destination slave id stored, i.e., for master 0 the destination id is in dest_slave[0], for master 1, it is in dest_slave[1] and so on.

Until here, all is well.

Then, say for master 0, I am using the dest_slave[0] value to index the the array of slave interfaces (s_ahb) and pick out that corresponding destination slave interface to probe a signal and use it in an assertion. But, now I am getting the error:

non constant array index into instance array

int dest_slave[NUM_MASTERS];
generate
  for (genvar i = 0; i < NUM_MASTERS; i++) begin
    always_ff @(posedge clk, negedge resetn) begin
      if (m_ahb[i].haddr >= 'h0000_0000 && m_ahb[i].haddr <= 'h0000_ffff) dest_slave[i] = 0;
      if (m_ahb[i].haddr >= 'h1000_0000 && m_ahb[i].haddr <= 'h1000_ffff) dest_slave[i] = 1;
      if (m_ahb[i].haddr >= 'h4000_0000 && m_ahb[i].haddr <= 'h4000_ffff) dest_slave[i] = 2;
    end
  end
endgenerate
generate
  for (genvar i = 0; i < NUM_MASTERS; i++) begin
    assert property my_proprty(m_ahb[i].hburst,s_ahb[dest_slave[i]]].hburst); //this line creates error it is not liking s_ahb[dest_slave[i]]
  end
endgenerate

Solution

  • My guess is s_ahb is a module instance or non-virtual interface instance. These types of arrayed paths cannot be dynamically accessed. You can create in logic to separate probing and mapping.

    int dest_slave[NUM_MASTERS];
    int slave_hburst_val[NUM_MASTERS]; // <- change data type as needed
    generate
      for (genvar i = 0; i < NUM_MASTERS; i++) begin
        always_ff @(posedge clk, negedge resetn) begin
          if (m_ahb[i].haddr >= 'h0000_0000 && m_ahb[i].haddr <= 'h0000_ffff) dest_slave[i] = 0;
          if (m_ahb[i].haddr >= 'h1000_0000 && m_ahb[i].haddr <= 'h1000_ffff) dest_slave[i] = 1;
          if (m_ahb[i].haddr >= 'h4000_0000 && m_ahb[i].haddr <= 'h4000_ffff) dest_slave[i] = 2;
        end
    
        assign slave_hburst_val[i] = s_ahb[i].hburst; // intermediate assignment
    
        assert property my_proprty( m_ahb[i].hburst, slave_hburst_val[ dest_slave[i] ] );
      end
    endgenerate
    

    FYI: your original code you has an extra ]. s_ahb[dest_slave[i]]].hburst