system-veriloguvmsystem-verilog-assertions

How to make a signal stable for quite some time in the assertion

Suppose I have an assertion as follows. Now here I want signal A to remain stable for some time after rising up. That is, A should be high until the first occurrence of D == 4 after that it can go low at any time it wants. Also I dont want to use ##[0:$] in this assertion.

Any help/advice would be very much appreciated. Thank you.

property p_check(A,B,C,D,E);
     @(posedge clk) disable iff(!resetn)
      $rose(A) ##1 B ##0 (C == 3) ##0 (D != 2) |=> (D == 4)[->1] ##[0:2] (!E throughout A);
   endproperty : p_check
Solution

  • You should write this as a separate property. 

     @(posedge clk) disable iff(!resetn)
    $rose(A) |=> $stable(A) until (D==4);