How to test sequential components properly with VUnit testing library and using VHDL? I've been using it to test combinatorial components using wait for statements etc. Example of it here in my github repo.
Obviously I've to generate a clock signal with clk <= not clk after half_period; but how to wait for it? Do I write something like wait until rising_edge(clk). But if I want to advance clock by multiple clock cycles? Is there better way than copy above line multiple times?
If you're using VUnit you already have such a procedure available. VUnit ships with the OSVVM library for its randomization features but it also contains other stuff, for example WaitForClock. To enable OSVVM you need to add the following in your Python script.
ui = VUnit.from_argv()
ui.add_osvvm()