verilogsystemsystem-veriloguvmsystem-verilog-dpi

Accessing internal modules(tb.dut.a.b) apb interface at top tb level


Is there any way I can connect an apb master vip to internal module inside dut which have apb signals in it . I want to program some registers in this deep inside dut module .

I tried to connect an interface and bind it at deep inside module , kind of working but I have to declare all the signals at interface as I/O’s and my simulator doesn’t like it , throwing lots of warnings about multiple driving .

Is there any other clean to way to access?


Solution

  • If the name of the internal module you want to bind to is fixed, you do not need ports in the bind module to communicate. Instead, you can use an upward name reference to the signals in the internal module (See section 23.8 in the LRM).

    For example suppose the internal module name is im, and the interface you want to bind is bi.

    module im(whatever port list);
    
      // internal signals
      logic [15:0] data;
      wire [15:0] add;
      logic [15:0] memory[16];
      ...
    endmodule
    interface bi();//no ports needed
      function void reset_memory;
          foreach (im.memory[e]) im.memory[e] = 0;
      endfunction
    endinterface