My processor is an STM32F746ZGT6 and I wish to use TCD132DG, so I need to generate two synchronous clock pulses with different frequencies (One of them is 2 MHz and the other one is 500 KHz) so I used two different timers in output compare mode. The problem is that these two pulses have phase shift. In the Datasheet of TCD132DG the maximum allowed time shift is 60ns while the pulses have 240ns time shift.
Thanks, Amir Reza
Set up the timers in a master-slave configuration so that enabling one timer starts the other. For example,
TIM1
master mode to send its Enable as trigger output (MMS=001
in the
TIM3->CR2
register).TIM2
to get the input trigger from TIM1
(TS=000
in the TIM2->SMCR
register).TIM2
in trigger mode (SMS=110
in the TIM2->SMCR
register).CEN
bit of TIM1->CR1
should start both timers at once.