system-verilog

Is there a way to 'map' arrays?

I'm looking for an elegant way to map entries in an array, other than a for-loop that creates a new array. For example

class A;
  int int_member;
endclass

A class_container[$];
int int_members_only[$];

initial begin
  // Assume class_container is populated

  // 'map' is not an available function 
  int_members_only= class_container.map(x) with (x.int_member);

  // Yes, you can do this but I want to know if there's another way
  foreach (class_container[i_class]) begin
    int_members_only.push_back(class_container[i_class].int_member);
  end
end
Solution

  • There is nothing in SystemVerilog that does this kind of mapping. The closest feature directly for your example is the streaming operator. (11.4.14 Streaming operators (pack/unpack)), but that only works if there is only one member in the class. I assume that is not the general case you need.