[SOLVED] Array of parameters in systemverilog

Array of parameters in systemverilog

I try to instantiate array of parameters, e.g.

module top();
    parameter array_size = 10;
    parameter par_array [array_size] = '{array_size{12}};

    initial begin
        $display("%d",par_array[array_size-1]);
    end
endmodule

But when I try to compile this module in questasim, I get this kind of error

-- Compiling module top ** Error: (vlog-13069) parameters_array.sv(3): near "[": syntax error, unexpected '[', expecting ';' or ','.

Search on this subject led me to the following topic and answerer says that systemverilog does allow this kind of construction.
I really don't want use long parameter vector, cause it's lead to new difficulties and this construction is compiling in Vivado (but for the sake of verification I need to use Questa).

Solution

parameter arrays are only supported in system verilog. So, make sure that you compile in the system verilog mode (file extension .sv or whatever qualifiers you need).

Also you'd better do int in your case:

parameter int par_array [array_size] = '{array_size{12}};`
----------^^^