Implicit net-type declaration and `default_nettype

I have a question on `default_nettype directive of SystemVerilog.

By default, the following code is ok.

module m1 (
   input  logic i1,
   output logic o1
   );

   logic  l1;
   assign l1 = i1;
   assign o1 = l1;
endmodule

However, when I change the default net type to none:

`default_nettype none

only i1 causes an error:

ERROR: [VRFC 10-1103] net type must be explicitly specified for i1 when default_nettype is none ...

Why does only input logic i1 cause an error and require explicit wire, but output logic o1 and logic l1 does not?

Verilog has too many implicit rules to accommodate lazy programmers (i.e. people who were interested in designing hardware, not writing software)

This error is explained in section 23.2.2.3 Rules for determining port kind, data type, and direction

For the first port in an ANSI style port list:

• If the port kind is omitted:
  • For input and inout ports, the port shall default to a net of default net type. The default net type can be changed using the `default_nettype compiler directive

This implicit 'net' port rule is the opposite of what is used when declaring output ports, and all other declarations outside of ports. The reason behind this is that input ports are an overwhelmingly majority of ports used in a module, and keeping ports connections as wires allows for port collapsing, which is more efficient for simulation.