In a simple module I have defined a 4-bit array register, and I use it to assign a value to a 4-bit array output. The output acts like a 1-bit wire even if it has been defined as a 4-bit array.
`timescale 1ns/1ps
module test(input in,
output wire [3:0] outpt);
reg [3:0] A = 4;
assign outpt = A;
endmodule
module testbench1();
test tst(in, outpt);
initial begin
$strobe("| %d | %d |",outpt,tst.A);
end
endmodule
When I run the testbench: If A = 5, then output will be 1. If A = 4 the output will be 0. Output acts like 1-bit even though I have defined it as 4-bit array.
I'm using .v files and the program Active HDL 10.2.
You explicitly declared outpt as 4-bit in test. Since you did not explicitly declare outpt in testbench1, it defaults to 1-bit. You should declare it as:
wire [3:0] outpt;
Some simulators will generate a warning message about this. Try your code on edaplayground.