I am writing some interfaces for my design in SystemVerilog, I have many of them. I was wondering if there are some specific guidelines regarding how to organize them.
right now I have all of my interfaces in one file. I was wondering if I should place each one of them in a separate file or all in one file. And if there are some specific guidelines on how to name the file(s).
Thanks.
Although the answer might seem opinionated, tools are designed with one file per design unit in mind, and the name of the file should match name of the unit. So if the name of the interfacer is foo, the name of the file should be foo.sv This way the tool can search a directory for files without having to specify them individually. The *.sv extension lets the tool know the file is writing in the SystemVerilog language.
Having one file per unit makes debugging easier and simplifies code coverage analysis. There might be other reasons with respect to project management for adhering to one file per unit, but those do get more opinionated.