Importing Custom VHDL IP but not able to use or view IP

I'm new to VHDL, and currently am working on applying a few filters to a hdmi pass through example code I found. I managed to get everything working (HDMI Pass Through with RGB Switch Filter) so I'm trying to migrate the code over to a piece of IP using Vivado.

I declared the component and instance like so:

component TestIP
        port (
            vid_pData         : in std_logic_vector(23 downto 0);
            vid_pData_new     : out std_logic_vector(23 downto 0);
            aRst              : in std_logic;
            PixelClk    : in std_logic;

            sw0               : in std_logic;
            sw1               : in std_logic;
            sw2               : in std_logic;
            sw3               : in std_logic   
            );

---

TestIP_inst : TestIP
port map(
    vid_pData => vid_pData_new,
    aRst      => async_reset_i,
    PixelClk      => pixelclk,

    sw0       => sw0,
    sw1       => sw1,
    sw2       => sw2,
    sw3       => sw3
    );

The rest of the code was kept the same. I packaged the IP using the IP wizard, and exported it to the default IP repository. It created a file called TestIP_0, with two files, TestIP_0 and Top_IP, both are .vhd files.

In the source hierarchy in vivado, I can see in the IP my instance, TestIP_inst: TestIP(Behavioral)(TestIP_0.vhd)

The issue is I cannot find this in my IP catalogue, and even though I can create a bitstream successfully on my schematic I was expecting to find my IP inbetween the DVI2RGB and RGB2DVI block, but instead my IP doesnt appear and the data stream isn't connecting the input to the output so when I program the board the screen is just black.

I apologise in advance for what is probably a stupid question, but any idea how to correct this?

Thanks

EDIT Here is my entity declaration of TestIP

entity TestIP is
Port ( vid_pData : in STD_LOGIC_Vector(23 downto 0);
       vid_pData_new : out STD_LOGIC_Vector(23 downto 0);
       aRst              : in std_logic;
       PixelClk    : in std_logic;

       sw0 : in STD_LOGIC;
       sw1 : in STD_LOGIC;
       sw2 : in STD_LOGIC;
       sw3 : in STD_LOGIC);
end TestIP;

The correct way to initiate the component was by defining a new set of variables, it must've been getting mixed up as there were multiple instances of vid_pData and vid_pData new, so there was no "order" to the flow of data.

TestIP_inst : TestIP
port map(
    vid_pData1  => vid_pData,
    vid_pData2 => vid_pData_new,
    aRst      => async_reset_i,
    PixelClk      => pixelclk,

    sw0       => sw0,
    sw1       => sw1,
    sw2       => sw2,
    sw3       => sw3
    );