Why does the V flag shown in the addition in assembly language below is set to 1 instead of 0? Why does the overflow occur?
Here is a question on a practice quiz that I did but I do not understand why the V flag is 1.
Solution
$83 = –125
$74 = 116
–125 – 116 = –241, which doesn’t fit in 8 bits. (The range of an 8-bit signed number is –128 to +127.) Since the result doesn’t fit, you get signed overflow, which sets the V bit.
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