system-verilogverilator

How do I cast to longint unsigned in systemverilog?

I want to cast logic packed array into longint unsigned in systemverilog and then I can export it using DPI-C to C++ unsigned long. The simulator I am using is Verilator. Check the example below.

logic[31:0] v1;
logic[63:0] v2;

int a = signed'(v1); //cast to signed int
int b = int'(v1); //cast to signed int
int unsigned c = unsigned'(v1); //cast to unsigned int
longint d = longint'(v2); //cast to signed long
//longint unsigned e = longint unsigned'(v2); //This doesn't work. I need to cast to unsigned long.
Solution

  • You need to create a SystemVerilog type without a space in it using typedef. Here's an example:

    // ..
typedef longint unsigned uint64_t;
uint64_t e = uint64_t'(v2);