I am doing some EDA tools test with cocotb as a testbench. I am running simulations with icarus and verilator without problem, however, with Aldec I have got a problem at "runsim.tcl".
The output of the console is
Welcome to VSIMSA!
This message was printed from `startup.do' macro file.
runsim.tcl(5) error: parse error
@if [string length<--
make[1]: *** [/c/users/mehdi/anaconda3/lib/site-packages/cocotb/share/makefiles/simulators/Makefile.aldec:176: results.xml] Error 1
make[1]: Leaving directory '/c/Users/Mehdi/testcocotbVerilator'
make: *** [c:\users\mehdi\anaconda3\lib\site-packages\cocotb\share\makefiles/Makefile.sim:82: sim] Error 2
I would appreciate if someone could advise me how to fix this
Your tag says active-hdl - then you should probably use the new SIM=activehdl from cocotb master.
SIM=aldec is for Riviera-PRO.