multi dimensional array ports support in icarus verilog

I am trying to use multi dimensional arrays as ports in my systemverilog code. the top module is a 3-dimensional array whereas the submodule is a 2-dimensional one. A simplified test bench and design is as follows:

  module TB();

      wire  [3:0]d_inAll  [0:99][0:9];
      wire  [3:0]d_outAll [0:99][0:9];

      genvar iX;
      for (iX=0; iX<100; iX=iX+1)begin
           someDesign DUT_i(.d_in(d_inAll[iX]) , .d_out(d_outAll[iX]));
      end

   endmodule

and the design is

module someDesign(input wire [3:0] d_in[0:9],
                  output wire[3:0] d_out [0:9]);

  genvar i;
  for (i=0; i<10; i=i+1)begin
    assign d_out[i] = d_in[i];
  end

endmodule 

I was trying to compile this code with icarus verilog but it fails with following error.

../elaborate.cc:1439: failed assertion rval_net->pin_count() == prts[0]->pin_count()

Is this a bug with the compiler or some feature not supported yet? is there any other method I could use to workaround the problem? I am aware I can flatted the arrays, however, I would prefer not to use it as it will make the design more prone to functional bugs.

It's a bug, therefore it's unsupported. It seems to support 1-D unpacked array ports, so you can move one of the array dimensions to the packed side.

module TB();

      wire  [0:9][3:0]d_inAll  [0:99];
      wire  [0:9][3:0]d_outAll [0:99];

      genvar iX;
  for (iX=0; iX<100; iX=iX+1)begin : fiX
           someDesign DUT_i(.d_in(d_inAll[iX]) , .d_out(d_outAll[iX]));
      end

   endmodule

module someDesign(input wire [0:9][3:0] d_in,
                  output wire[0:9][3:0] d_out);

  genvar i;
  for (i=0; i<10; i=i+1)begin
    assign d_out[i] = d_in[i];
  end
endmodule