verilogxilinxvivadovlsiiverilog

Why the vivado 2017.4 is showing error here?

My code is:

module circuilar_fifo;
localparam B=3,W=2;
input wire clk,reset,wr,rd;
input wire [B-1:0] wr_data;
output wire [B-1:0] rd_data;
output wire full,empty;

Isn't this one of the correct method of declaring input outputs? But why does the Xilinx vivado 2017.4 webpack edition is showing that

port rd_data is not defined

Why is it showing like this? Where am I went wrong? I could've designed the code in

module circular_fifo(
input wire [B-1:0] wr_data;
input wire clk,reset
............
 );

But what is wrong in 1st coding design?

Solution

  • In the first style, the module header needs a list of port names thus:

    module circular_fifo(clk, reset, wr, rd, rd_data, wr_data, full, empty);