For example (from the IEEE Std 1800-2017, section 7.4.5 Multidimensional arrays):
bit [1:10] v1 [1:5]; //1 to 10 varies most rapidly; compatible with memory arrays
bit v2 [1:5][1:10]; //1 to 10 varies most rapidly, compatible with C;
If you line up all the elements by their order in memory(or as a bit-stream), the dimension whose index whose index that would change between each element is the one that varies most rapidly. The memory layout does not matter so much since SystemVerilog has no pointers. But is does matter when you try to select parts of an array, the index selecting goes from least to most varying.
v1[2][3]
is 2 of 5 followed by 3 of 10.