I understand that if I want to include all the Verilog files, I can do so by adding files like this:
iverilog /Users/kp/Desktop/all_new2/*.v -s testbench.v
which takes all files in all_new2 folder and sets testbench.v as the top module. However, I wish to exclude a file c_functions.v file from this folder. How do I do it?
One way is to use the -y <libdir>
option, which is common among other simulators as well. This is described in the iverilog Command Flags/Arguments document.
iverilog -y /Users/kp/Desktop/all_new2 testbench.v
This will compile only those modules that are needed in the directory. There is no need to explicitly list out all files.