In a modified Harvard architecture, both data and instructions (code) are stored together in DRAM and in L2 cache, while being separate at the L1 level. They are also both transferred from DRAM to cache through the data bus. I read that there can be separate memory controllers for data/instructions. But is there a subdivision of the bus lines into data and instructions?
And if they are separate, what are the trade-offs of having split bus lines vs unified lines? are they physically implemented differently or are they fungible?
External bus lines, no. That would be full Harvard, not just split L1.
"Modified Harvard" is just a speed hack for a von Neumann architecture, with the only visible effect being that you need to run a cache-sync instruction for self-modifying code / JIT code-gen to work reliably.
(Unless you have an ISA like x86 that requires L1i + the pipeline to be coherent with data caches, in which case stores have to snoop in-flight code addresses...)
See:
There are some chips with separate busses for instructions and data.
You typically find that true-Harvard setup in cache-less microcontrollers where instructions are fetched from ROM (or NOR flash or something), while data load/store uses SRAM or DRAM.
Some, like AVR, have a load-program-memory (LPM) instruction, so you can have read-only constant data (like lookup tables) in EEROM / flash. Different external busses can be hooked up to different types of memory. If supported, SPM (Store program memory) can even write to that memory, for persistence across power cycles, although limited write-endurance of such memory means you don't want to do that as part of normal operation. Having an LPM instruction means it's a bit less pure Harvard, but it's apparently not available on all AVR devices. But if you do have it, it's more like separate busses for flash vs. RAM, with ability to load/store data to either. But you can only execute from program memory, so it's not full von Neumann unless SPM is also supported.
Two separate address-spaces also means you can address e.g. 64k of code and 64k of data, instead of 64k total, with 16-bit addresses.