verilogsystem-verilogtest-benchvlsi

Does SystemVerilog Generate support delays?

I thought of generating clock using genvar like below:

        reg [7:0]clk;  
      
     genvar i;
        generate
          for (i=0; i < 7; i++) begin
              #1 clk[i]=~clk[i];
            end
        endgenerate

I am getting an error:

error: near "#": syntax error, unexpected '#'

How can we resolve it? Can I use delays inside generate block?

Solution

  • Yes, generate blocks support delays. To fix your problem, use a procedural always block:

    reg [7:0] clk;  

genvar i;
generate
    for (i=0; i < 7; i++) begin
        always #1 clk[i]=~clk[i];
    end
endgenerate