I am learning the assembly language of cortex m3, I don't understand why the reset is start + 1, it should be start only know as to when reset it should execute from start and is there any special reason that sp is assigned 0x200.
.thumb
.syntax unified
sp: .word 0x200
reset: .word start + 2
start:
mov r0, #5
mov r1, #4
add r2, r0, r1
stop: b stop
That is a bit of a bug as written in more than one way. The arm documentation clearly states that vectors are the address with the lsbit set so one can think plus one but it is safer to OR with one.
The cortex-m3 if/when you read up on it, is armv7-m based, and in the armv7-m documentation which you should also have before doing any kind of programming like this then:
On powerup or reset, the processor uses the entry at offset 0 as the initial value for SP_main, ... All other entries must have bit[0] set to 1
On exception entry, if bit[0] of the associated vector table entry is set to 0, execution of the first instruction causes an INVSTATE UsageFault
(yes that means all exception vectors not just reset)
Let the language work for you and you won't have to hack at these bits, the tools will do it for you:
.thumb
.syntax unified
sp: .word 0x200
reset: .word start
.thumb_func
start:
mov r0, #5
mov r1, #4
add r2, r0, r1
stop: b stop
Once linked (the table can't be filled in until linked and the linker knows that label is a function so generates the proper value).
Disassembly of section .text:
00000000 <sp>:
0: 00000200 andeq r0, r0, r0, lsl #4
00000004 <reset>:
4: 00000009 andeq r0, r0, r9
00000008 <start>:
8: f04f 0005 mov.w r0, #5
c: f04f 0104 mov.w r1, #4
10: eb00 0201 add.w r2, r0, r1
00000014 <stop>:
14: e7fe b.n 14 <stop>
And you can see that the vector table is proper and will function, the reset vector points at the reset handler start: ORRed with 1 (0x00000008|1 = 0x00000009)