Why PC in RISC V architecture connect with PC+4 instead of PC+2 or PC+1. I think it depend on the width of memory cell of the Instruction Memory (IMEM). If the width is 16 bits, then we need to load two adjacent addresses to fill 32 bits instruction or if the width is 32 bits, we only need to load one address to take the full instruction.
RISC-V deals with everything in byte addresses (from page 19 of the ISA manual: "RV32I provides a 32-bit user address space that is byte-addressed and little-endian"). So when using byte addresses, it makes sense to think of the PC as incrementing by 4, as each of the RV32 instructions are 4 bytes.
When we say RISC-V increments the PC by 4, what that means is that for any given byte address X of a 32-bit RISC-V instruction, the next instruction will begin in memory at address X+4. (Note that when using compressed instructions, which are 16 bits / 2 bytes, the PC is incremented by 2).
An IMEM read width of 16 bits means 2 reads from IMEM are necessary to get a full instruction, and an IMEM read width of 32 bits means only 1 read from IMEM is necessary to get a full instruction. But these are implementation considerations, not an ISA considerations -- you could hypothetically implement an ISA-compliant RISC-V processor with either type of IMEM.