Verilog Synthesis Error (Synth 8-151): Case item is unreachable

I'm writing a Verilog module for a simple FSM that has 6 possible states. The module has 4 Moore outputs and 7 inputs from other modules. I'm using a case statement to determine the next value of the state however I'm getting the synthesis errors

[Synth 8-151] case item 3'b100 is unreachable [line 40]

and

[Synth 8-151] case item 3'b101 is unreachable [line 41].

Line 40 is pointing to SCLEAR: nS = Done ? SCLEARRET : SCLEAR;

Line 41 is pointing to SCLEARRET: nS = allDone ? SWAIT : SCLEARRET;

These errors are causing the FSM not to be able to send out the shipClr variable.

Here is the entire module:

module SSStateMachine(shipGRB, Done, Go, clk, reset, allDone, Ready2Go, Stop, nextLED, delay,lost, Clr, shipClr);
    output  shipGRB, Ready2Go, delay, shipClr;
    input   allDone, Done, Go, Stop, nextLED,lost,Clr;
    input   clk, reset;

    reg [1:0]   S, nS;
    parameter   SWAIT=3'b000, SSHIP=3'b001, SRET=3'b010, SDELAY=3'b011, SCLEAR=3'b100, SCLEARRET=3'b101;

    // Set the next state on the rising edge of the clock
    always @(posedge clk) begin
        if(reset)
            S <= SWAIT;
        else
            S <= nS;
        end

    // Determine the next value of the state based on the inputs
    always @(Go, Clr, Stop, Done, allDone, lost, nextLED) begin
        case(S)
            SWAIT:      if(Go)         nS = SSHIP;
                        else if(Clr)   nS = SCLEAR; 
                        else           nS = SWAIT;  
            SSHIP:      nS = Done    ? SRET     : SSHIP;
            SRET:       if(allDone) begin
                             if(Stop || lost) nS = SWAIT;
                             else             nS = SDELAY;
                             end
                        else nS = SRET;
            SDELAY:     nS = nextLED ? SSHIP     : SDELAY;
            SCLEAR:     nS = Done    ? SCLEARRET : SCLEAR;                       
            SCLEARRET:  nS = allDone ? SWAIT     : SCLEARRET;
            default:    nS = SWAIT;
        endcase
        end

    // Assign the outputs
    assign Ready2Go = (S==SWAIT);  // okay to press Go
    assign shipGRB  = (S==SSHIP);  // send data bits
    assign shipClr  = (S==SCLEAR);
    assign delay    = (S==SDELAY);
endmodule

Description of input the variables:

Done: from other module telling the FSM it can transition to SRET or SCLEARRET

allDone: from other module telling the FSM it can leave SRET or SCLEARRET

Go: Pushbutton

Stop: Pushbutton

Clr: Pushbutton

nextLED: from other module telling the FSM it can transition from SDELAY to SSHIP

lost: from other module telling the FSM it can transition from SRET to SWAIT

I have redrawn the transition chart multiple times, stepped through the case statement, tried rewriting it and still cannot find what the error may be. I don't understand how the states SCLEAR and SCLEARRET and unreachable. If Clr is pressed, and it is in state SWAIT shouldn't the FSM transition into SCLEAR?

Since you have 6 states, your state variables must be 3 bits wide, not 2 bits. Change:

reg [1:0]   S, nS;

to:

reg [2:0]   S, nS;

Also, your explicit sensitivity list is missing the S signal. You could replace your list with the implicit list. Change:

always @(Go, Clr, Stop, Done, allDone, lost, nextLED) begin

to:

always @*

This compact syntax automatically uses all the signals you need.